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Browse All TagsWorkshop on Static Timing Analysis and PnR
IEEE CEDA in collaboration with SILICON (Dept. of ECE) and Dept. Of EEE presents
Clock To Chip
Workshop on Static Timing Analysis (STA) & Placement and Route (PnR).
Turn your RTL dreams to silicon reality!
Distinguished Speakers
Lunch and snacks will be provided.
IEEE goodies included.
Open to ALL branches.
Registration Fees
Registration Deadline: April 16, 2026 (Thursday)
Register Here
ADCOM 2027: Multi-Agent Systems and Decentralized Intelligence
31st International Advanced Computing and Communication Conference
Leading with Ethics, Integrity & Purpose
Orientation of Student Tech Forum Silicon
The Central Library and Department of Computer Science & Engineering (Artificial Intelligence & Machine Learning),
Faculty Development Program
